introduction
EDA technology is a design method based on large-scale programmable logic devices and hardware language as the main method of system logic. It uses computer, large-scale programmable logic device development software and experimental development system as design tools, and through related development software. Automatically complete the design of electronic systems to hardware systems designed with software, and finally form a new technology for integrated electronic systems or dedicated integrated chips. Its design flexibility allows EDA technology to be rapidly developed and widely used.
This article uses Max+PlusII software as the design platform and uses VHDL language to realize the overall design of digital frequency meter.
1 Working principle
As is known, the frequency signal is easy to transmit, and the anti-interference is strong, and good measurement accuracy can be obtained. Therefore, frequency detection is one of the most basic measurements in the field of electronic measurement. The basic principle of the frequency meter is to use a frequency source with high frequency stability as the reference clock to compare the frequencies of other signals. Normally, the number of pulses of the signal to be measured per second is calculated, that is, the gate time is 1 s. The gate time can be valued according to needs, and it can be greater than or less than 1 s. The longer the gate time, the more accurate the obtained frequency value, but the longer the gate time, the longer the interval between each frequency. The shorter the gate time, the faster the measured frequency value is refreshed, but the measured frequency accuracy is affected. Generally take 1 s as the gate time.
The key components of the digital frequency meter include the frequency control signal generator, counter, latch, decoding drive circuit and display circuit. The block diagram is shown in Figure 1.
2 Design analysis
2.1 Frequency Control Signal Generator
The frequency control signal generator generates the control timing of the measurement frequency, which is the key to designing the frequency meter. Here, the control signal CLK is taken as 1 Hz, and after dividing by 2, it is a clock signal FZXH with a pulse width of 1 s, which is used as a counting gate signal. When FZXH is high, it starts counting; on the falling edge of FZXH, a latch signal SCXH is generated. After the data is latched, the clear signal CLEAR is generated before the next rising edge of FZXH to prepare for the next count, CLEAR The signal is valid on the rising edge.
2.2 Counter
The counter uses the signal to be tested FZXH as the clock. When the clear signal CLEAR arrives, it is asynchronously cleared. When FZXH is high, the counting starts. The maximum counter count designed in this article is 99 999 999.
2.3 Latch
When the rising edge of the latch signal SCXH comes, the counter value of the counter is latched, so that it can be decoded by an external seven-segment decoder and displayed on the digital tube. The advantage of setting the latch is that the displayed data is stable and will not flash continuously due to the periodic clear signal. The number of bits in the latch should be exactly the same as the counter, which is 32 bits.
2.4 decoding drive circuit
In this paper, the digital tube adopts the dynamic display mode, and only one digital tube can be lit at a time. The digital tube's bit selection signal circuit is a 74LS138 chip, and its 8 outputs are respectively connected to the 8 digital tube bits; the 3 inputs are respectively connected to the I/O pins of the EPF10K10LC84-4.
2.5 digital tube display
In this paper, eight common cathode digital tubes are used to display the value of the frequency to be measured, and the display range is from 0 to 99 999 999.
The following is the procedure for selecting the digital pipe segment:
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