For analog CMOS (complementary symmetric metal oxide semiconductor), the two main hazards are static electricity and overvoltage (signal voltage exceeds the power supply voltage). Understand these two major hazards, users can effectively deal with.
Static electricityThe damage caused by the electrostatic voltage formed by electrostatic charge build-up (V=q/C=1 kV/nC/pF) may break through a thin layer of insulating oxide (or nitride) between the gate and the substrate. This hazard is very small in a normally operating circuit because the gate is protected by an on-chip zener diode, which can deplete the charge to a safe level.
However, when inserting a socket, there may be a large amount of static charge between the CMOS device and the socket. If the first pin of the plug socket does not happen to be connected to the zener diode protection circuit, the charge on the grid will be released through the oxide layer and damage the device.
The following four steps help prevent the device from being damaged during the system assembly phase:
Store unused CMOS devices in black conductive foam to prevent charge build up between pins when shipped.
The operator responsible for the device plug-in should be connected to the system power ground through a plastic grounding strap.
Before removing the CMOS device from the protective foam, the foam should share the ground with the power supply to release the accumulated charge.
After the circuit is inserted into the board, the board should be grounded or shielded when moving the board.
SCR latchWhen using an analog CMOS circuit, the safest method is to ensure that no analog or digital voltage exceeding the supply voltage is applied to the device and that the supply voltage is within the rated range. However, it is also necessary to carry out overvoltage protection. If you understand the mechanism of the problem, protection measures will be effective in most cases.
Figure 1 is a circuit diagram and cross-section of a typical CMOS output switching unit. From the connection relationship between different cells and regions, we can draw an equivalent diode circuit diagram (Figure 2). If the analog input voltage at the S-side or the D-side exceeds the power supply voltage.
Figure 1: Circuit diagram and sectional view of a typical CMOS output switching unit
Figure 2: Equivalent Diode Circuit Diagram
Parasitic transistors produced by different diode junctions are in forward biased mode. These parasitic NPN and PNP transistors form an SCR (silicon controlled rectifier) ​​circuit as shown in FIG.
Figure 3. Parasitic transistor benefits in CMOS switching
Overvoltage can cause excessive current and metallization problems. In general, the output of the operational amplifier acts as a voltage source for the S-side or the D-side, so the current cannot exceed the limit of the DC output current of the op amp. However, transient induced currents can still damage CMOS devices; therefore, protection is necessary.
FIG. 4 illustrates a method of preventing parasitic transistor conduction by connecting a series diode (eg, 1N459) to a power supply pin. If the voltage at the S terminal or the D terminal is higher than the power supply voltage, CR1 and/or CR2 are reverse biased and the base drive circuit cannot turn on the transistor. Each CMOS device should have a pair of independent diodes to protect it. Although this method is effective, it is not foolproof. If one end of the switch is connected to a negative potential (for example, a charging capacitor) and the voltage at the other end exceeds VDD, there is a protection diode.
Figure 4: Circuit Protection Scheme
An emitter's avalanche diode at Q2 is sufficient to provide a base drive to turn on Q2. For this case, there must be a current-limited power supply or resistor in series with the capacitor.
If there is a transient overvoltage at the S-side or the D-side, the series resistance at the port powered by the voltage source is recommended to be 300 to 400Ω (Figure 4b).
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