Abstract: With the development of system-on-chip (SoC) to network-on-chip (NoC), energy consumption has gradually become the primary limiting factor in chip design. Through the establishment of CMOS circuit and network communication at two different levels of power consumption model, from the different design levels of integrated circuits, on-chip network communication power consumption and NoC mapping issues, NoC low power design, comprehensive analysis of NoC low power consumption Design method.
Introduction: As the number of transistors integrated on a single chip exceeds the order of one billion, energy consumption has gradually become the primary limiting factor in chip design. The design focus of integrated circuits has also changed from chip functional requirements to power consumption requirements. As the future development direction of chip design, NoC is of great significance to study its power consumption. 　
1 Power consumption model
1. 1 CMOS logic circuit power consumption model
The power consumption of integrated circuits is mainly composed of four aspects: dynamic power consumption, short circuit power consumption, static power consumption and leakage current power consumption.
(1) Dynamic power consumption is caused by the charging and discharging behavior of the node capacitance in the circuit, which can be expressed by the following expression:
In the formula: Vdd is the power supply voltage; Ci is the node capacitance to be charged and discharged; i is the node activity factor (representing the ratio of the average number of charge and discharge of the node capacitance to the switching frequency); f is the switching frequency.
(2) The short-circuit power consumption is formed by the short-circuit current generated by the power supply to ground under certain conditions, and its expression is:
Where: k is determined by the process and voltage; W is the width of the transistor; Ï„ is the rise / fall time of the input signal; f is the switching frequency.
(3) Static power consumption is the power consumption formed when the circuit is stable.
(4) Leakage current power consumption refers to the power consumption caused by sub-threshold current and reverse bias current.
In integrated circuits that are dominated by static CMOS circuits, dynamic power consumption is the main component of the overall circuit power consumption, followed by short-circuit power consumption, and static power consumption and leakage current power consumption can be ignored in most cases [23] .
Analysis of the composition formula of dynamic power consumption can lead to methods such as reducing the power supply voltage, reducing circuit node capacitance and node switch activity, thereby reducing the power consumption of the integrated circuit.
The dynamic power consumption of an integrated circuit is proportional to the square of the power supply voltage. Therefore, reducing the power supply voltage can greatly reduce power consumption. However, the general power supply voltage Vdd should not be less than 2 ~ 3 times the threshold voltage Vt. If the power supply voltage is close to the threshold voltage, the delay of the circuit will be significantly increased. Therefore, in order to ensure the performance of the circuit, an appropriate low Threshold voltage V t. However, V t cannot be reduced without limit, and a certain noise margin must be maintained, and when V t decreases, the power consumption due to leakage current also increases accordingly.
On the other hand, considering the dynamic power consumption is caused by the charging and discharging behavior of the node capacitance in the circuit, the frequency of node charge and discharge is an important parameter, and the node activity factor is the parameter that reflects the frequency of node charge and discharge It is the product of the node activity factor and the node capacitance. To avoid useless charging and discharging behavior, the use of various low-activity circuit structures can reduce power consumption.
1. 2 On-chip network communication power consumption model:
Orion's power model (Power Model) is the first power model to be used in the network. Network on Chip (NoC) introduces the principles of network communication into the design of system-on-chips, and is suitable for Power Model power consumption models. The power consumption of the on-chip network communication refers to the power consumption of data communication between any resource nodes of the on-chip network. The power consumption of transmitting a data chip (f lit) in the Power Model power consumption model is expressed by Eflit.
In the formula: Ebuf represents the power consumption of the buffer; E ar b represents the power consumption of the arbitration; E xb represents the power consumption of the crossbar (Crossbar); Ecn = Ebuf + Earb + Exb represents the power consumption inside the communication node; Elnk represents the channel (link ) Power consumption. Assuming that H represents the number of network hops that the data slice passes through, the power consumption of the data slice (f lit) transmitted from the resource node Ri to the resource node R j:
When H = D, the power consumption at this time is the lowest, namely:
Here, D is the Manhattan distance obtained by the algorithm from the source node to the destination node using the shortest path.
2 Ways to reduce power consumption:
2. 1 Different design levels of integrated circuits:
Literature [5] introduces a low-power method at the design level of process-level low-power design and optimization technology. The layout-level low-power design and optimization technology is based on the Elmore model. The main power consumption of the optimized circuit is the power consumption of the interconnect. Placement and routing technology has evolved from considering only the factors of area and delay to the optimization of power consumption by adding signal activity information from the design front end. Gate-level low-power design and optimization techniques include timing adjustment, common factor extraction, process mapping, gate size optimization, and path balancing [67]. The timing adjustment (Ret iming) method introduced in [6] reduces the power consumption by inserting a new register or rearranging the position of the register to reduce the gate flip frequency or the longest delay through the pipeline. Literature [7] uses the common factor extraction method to achieve low power consumption of multi-level circuits. The process mapping method hides the node with a high turnover rate inside the gate unit with a small load capacitance, thereby reducing power consumption. The door size optimization method is to reduce the size of the non-critical path door to reduce the area and power consumption. The path balancing method saves power consumption by avoiding unnecessary false transitions. RTL structure-level low-power design and optimization technology This level of low-power methods include logic synthesis and optimization technology and parallel design (Parallism) and pipeline design (Pipeline) technology. Parallel design and pipeline design are to increase performance and reduce power consumption by increasing the area. After using the parallel design, the circuit area increases n times, the capacitance increases n times, the corresponding frequency and voltage decrease n times, because the power consumption and voltage The square of is proportional to, so the power consumption can be reduced by n2 times. System-level low-power design and optimization technology This level of low-power technology includes software and hardware partitioning, memory optimization [8], instruction-level optimization, dynamic power management [9], and bus low-power design.
2. 2 On-chip network communication:
2. 2. 1 Internal buffer power consumption:
When contention occurs, an internal buffer is needed to temporarily store low priority packets. In the switch structure circuit, the cache is usually realized by shared static RAM or dynamic RAM memory. The energy consumed by memory access is determined by competition between input packets. Destination competition is independent of application, no matter what switch structure system is used. The interconnection competition depends on the switch structure system, and different system topologies will produce different competitions. Therefore, the power consumption of memory access can be improved by optimizing the topology design.
2. 2. 2 channel power consumption:
Assuming there is a toggle switch based on the RailtoRail structure, the bit energy Eln k on the channel can be calculated by the following formula:
Where: Cw ire is the line capacitance of the channel, and Cinput is the total capacitance of the input gate connected to the interconnect. Cw = Cwire + Cinput is the total load capacitance of bit propagation.
The charging and discharging behavior of the interconnect capacitance determines the power consumption of the channel interconnect. Therefore, two technologies can be used, one is to reduce the switching activity as much as possible, and the other is to use low-power coding technology based on Hamming distance.
2. 2. 3 Switching power consumption:
Different switch structures have different effects on network performance (such as delay, throughput, power consumption, etc.). The following analyzes the power consumption problem in the switching structure and the power consumption estimation method for the switching structure system with different numbers of exits and entrances.
2. 2. 3. 1 Crossbar switch structure [10]
The Cr ossbar topology uses a space division multiplexer for the connection between input and output. As shown in Figure 2, each input and output connection has its own dedicated data path, therefore, the Crossbar structure has no interconnection competition. As the number of input and output ports increases, the power consumption of the switch will increase linearly. For a switch structure with a large number of ports, the power consumption will be very high.
2. 2. 3. 2 Fully connected network [10]:
Similar to Cro ssbar networks, there is no interconnection competition in fully connected networks, and no internal buffers are used in their power consumption models. The bit energy of each fully connected switch network is consumed on the interconnection line and the multiplexer. The complexity of the multiplexer is more complicated as the number of input terminals increases, and the power consumption also increases.
2. 2. 3. 3 Bany an network [10]:
The n-dimensional Bany an network has N = 2n inputs and N = 2n outputs. The total number of switches in n stages is 1/2 N! log2 N, and each stage is represented by i (0? i? n). In the Banyan network, the same interconnection may be shared by different data paths, so there is an interconnection competition problem, and a buffer needs to be set in each internal node switch.
The binary switch in the Banyan network is more complicated than the cross-node switch in Crossbar. When the bit data is switched from the input port to the output port, the binary switch consumes more energy.
2. 2. 3. 4 BatcherBanyan Network [10]:
The structure consists of a combination of Batcher sorting network and Banyan network, in which the competition problem is solved by Batcher sorting network, followed by Banyan network. In a sorted network, each input-output competition has its own dedicated path, so there is no interconnection competition problem.
Although the Batcher Bany an network solves the interconnection competition problem, it comes at the cost of increasing the number of stages between input and output. It has a total of 1/2 (log2 N) (log2 N + 1) stages, which will increase the bit energy in Consumption on switches and interconnects.
The interconnection competition causes a large amount of energy consumption in the internal buffer. As the throughput increases, the power consumption in the buffer will increase sharply. For a switch structure with a small number of ports, the internal node switch power consumption is the main factor. For a switch structure with a large number of ports, the interconnect line power consumption will dominate.
Different switch switching structure systems have different power consumption main bodies. According to different application requirements, the chip can be divided into several parts as a whole. Each part adopts different topologies to achieve chip performance, area and power consumption. Organic unity.
2. 3 NoC mapping problem:
NoC mapping is based on the given IP core library and task map, with certain design constraints (such as delay and power consumption) as the limiting conditions, each task is assigned to the appropriate IP core and each IP core is arranged The order of execution of the tasks, and then determine the location of each IP core in the NoC topology. During mapping, the search space increases with factorial growth as the network size grows. For a NoC with N IP cores, there are N! Possible results for the mapping. Therefore, the mapping problem is an NPcomplete problem.
The mapping problem of power consumption priority is to assign each processing unit in the application characteristic graph to the NoC resource node based on the given application characteristic graph and NoC topology structure graph, and to minimize the communication power consumption of the entire system. The ant colony algorithm as a typical biomimetic algorithm is widely used in solving NoC mapping problems.
3 Conclusion:
NoC is the direction of future chip development, and power consumption is a key issue in Noc design. This research starts from different power consumption models, discusses the low-power design of NoC from different design levels of integrated circuits, on-chip network communication functions, and NoC mapping issues. Consumption research made a more comprehensive classification analysis.
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