[Photo] BT1043B single-chip 900MHz RF transceiver

Fully integrate the RF transceiver front end into one chip;

BT1704B is a monolithic integrated RF transceiver using BiCMOS technology. Its RF input / output signal range is 890 MHz to 940 MHz, and this frequency band is most suitable for digital cordless phones. In addition to the input I / Q interface, the chip also contains all the required components that make up the RF-IF transceiver. Includes 2 local oscillators, 1 low-noise amplifier (all noise figures are less than 3.5dB, independent of temperature and power supply voltage changes), 2 high-linearity down-conversion mixers, 1 IF amplifier, 1 One up-conversion mixer and one internal power amplifier (-2dBm + 14dBm). BT1074B can operate normally within the range of 2.7 and 3.3V power supply voltage.

Table 1 Performance specifications

Table 2 Absolute maximum rate

Table 3 Pin definition

RF differential input pin. These two are the differential input pins of the LNA and need to connect a 10 picofarad AC coupling capacitor. The RF differential input signal is generated by an external phase-splitting circuit and matching circuit (see application circuit diagram). In order to obtain optimized performance, the device lead length of the external phase circuit and the PCB trace to the LNA input pin should be minimal. In addition, the ground plane must surround the split-phase circuit to prevent noise coupled by other circuits. Its frequency range is 800-1000 MHz.

First-order IF differential output pin. It is the differential output of the internal IF buffer; together with the external IF combiner circuit (see application circuit diagram), the differential output signal becomes a single-ended output, driving a 150 MHz BPF SAW filter. These internal IF buffers are open-drain output signals that drive a 700-ohm input impedance band-pass filter (BPF) through an external combiner circuit.

The second-level IF amplifies the input pin. Connect the output of a 150 MHz BPF SAW filter to this pin as a two-level down conversion. There is no need for AC coupling here.

Second-order IF differential output pin. It is the second-order differential output of the IF amplifier. Connect MIXEROUTP to ground with a resistor to control the gain value of the IF amplifier. If the resistance is 470 ohms, the gain value is 0dB. The other outputs of the amplifier (such as MIXOUTN) are supplied to a 10.7 MHz band-pass filter through a 0.1 microfarad AC coupling capacitor.

External clock input pin. Connect a 139.3 MHz clock and down-convert the first-order IF from 150 MHz to 10.7 MHz. There is no need for AC coupling here.

LNA power supply pin. This pin can provide power for the first and second level of the LNA. Because the input signal level of the LNA is small at high frequencies, the VDDLNA pin must be very close to the chip for decoupling (for example, within 0.25 inches).

LNA ground. The GNDLNA1P / N pin is the ground wire of LNA level 1, and GNDLNA is the ground wire of LNA level 2. The GNDLNA1P / N pins are separated internally. In order to obtain stable and optimized performance, the GNDLNA1P / N pin must be physically grounded.

Down converter power pin. This pin provides power for the down-conversion mixer.

Downconverter ground. This pin is the ground wire of the down-conversion mixer. It is recommended to use the bottom ground plane for grounding.

Power pins for IF buffer and two-level down-conversion mixer. Both power supplies require a 0.1 microfarad bypass capacitor to ground.

Ground of IF buffer and second-level down-conversion mixer. GND-IF is the ground wire of the internal IF buffer, and GNDRX-BUF is the ground wire of the two-stage down-conversion mixer and IF amplifier.

Power amplifier output pin. This pin is the differential output of the power amplifier and needs to be configured with a combination circuit (see application circuit diagram). The combiner can convert the differential signal into a single-ended signal, while providing a 50 ohm matched impedance. Because it is an open-collector output signal, it needs a DC bias to VDD, and it needs AC coupling at the rear of the combiner.

Preamp output pin. This pin is the differential output of the preamplifier and is an open collector signal. The preamplifier can be adjusted to the desired frequency band through two inductors connected to VDD. The recommended value in the application circuit diagram is 900MHz. Since this signal is also used as the input of the power amplifier, the connected inductor must be close to the pin and isolated from the output of the power amplifier to avoid output feedback from the pin. This output feedback will affect the stability of the power amplifier.

Preamplifier / amplifier bias / gain adjustment pin. REXT1 is the bias resistor used for the preamplifier; REXT2 is the bias resistor used for the power amplifier. For a power output of 14 dBm, it is recommended to use 330 ohms for REXT1 and 4.7K ohms for REXT2. If the resistance of REXT1 is increased or the resistance of REXT2 is decreased, the power output will be reduced, and vice versa.

Baseband data input pin. This pin is an input interface for data signals from DSP or μP. TXI and TXQ are in-phase and quadrature signals, respectively, and M-REF is a DC signal from DSP or μP. All of the above pins need to have a DC level of VDD / 2, and a voltage swing of 500mVp-p is required for TXI and TXQ. The application circuit diagram shows the attenuation of 1Vp-p I / Q signal and 6dB voltage Connect the DC reference to the M-REF pin.

The power supply pin of the power amplifier protection ring. This pin is only used for the output of the power amplifier. Before it is shared with other power supplies, it must be decoupled at this pin.

Preamp power supply. If possible, it is necessary to properly decouple this pin from the ground plane.

RF up-conversion mixer power supply. If possible, it is necessary to properly decouple this pin from the ground plane.

Input buffer and IF up-conversion mixer power supply. In addition to the usual high frequency decoupling, the low frequency must also be decoupled, with an upper limit of 10 MHz.

(Pin 7/9/11, 13/15/18, 22/23, 27)

The above pins are used for power amplifier, preamplifier, RF up-conversion mixer, input buffer and IF up-conversion mixer ground.

RF VCO input control pin. A resonant circuit must be connected externally (see application circuit diagram). This resonant circuit can generate all oscillator frequencies for RF VCO, so it must be optimized to avoid interference caused by other devices. This pin and the external PLL (phase-locked loop) form an RF-PLL loop that can generate a fixed oscillator frequency for the RF VCO.

RF VCO output pin. This pin is connected to an external PLL to form an RF-PLL loop. The PLL applies a DC voltage to the input resonant circuit based on the detected RF-VCO-OUT signal. This DC voltage can generate the negative bias required by the varactor and generate the necessary capacitance for the resonant circuit network.

RF VCO input stage power and ground. For optimal performance, VDDRFVCOIN must be routed to GNDRFVCOIN through a low-inductance high-frequency coupling capacitor. The input stage of the RF VCO is critical in generating all the frequencies required by the RF VCO, so isolating these power pins will enhance the overall performance of the RF VCO.

RF VCO power and ground. This pin provides power for other stages of RF VCO.

RF VCO feedback capacitor input. This pin provides an off-chip capacitive feedback loop for RF VCO.

IF VCO input pin. This pin is connected to an external resonant circuit and the frequency is adjusted to 560MHz.

IF VCO differential output pin. This pin is an open collector output signal and must be connected to an external power supply through a 50 ohm resistor. The oscillation frequency of this VCO can be controlled by connecting any of the differential output pins to the PLL (see application circuit diagram).

VCO input power pin. IF VCO has 2 power supplies, namely VDD-IFVCOIN and VDDIF-VCO. The former is the power supply of the first-level VCO. It is recommended to connect a large capacitor of at least 100 picofarads between this pin and ground to filter out noise.

VCO cache power pin. Power supply for internal VCO cache circuit.

VCO input ground pin. It is the first-level VCO ground.

VCO ground. It is the ground wire of the internal VCO circuit.

VCO feedback capacitor input pin. Provides an off-chip capacitive feedback loop for the VCO oscillator.

Send output power control pin. This pin controls the power amplifier to 2 levels, the HIGH signal places the power in low power mode (output power is -2dB), and the LOW signal places the power in high power mode (output power is + 14dB). These power levels are based on the resistance of REXT1 and REXT2.

Transmitter amplifier power-down control pin. This pin can control the power amplifier and preamplifier, its HIGH signal can turn on the above amplifier, and its LOW signal turns them off.

Transmitter power-down control pin. This pin controls the power-down function of the entire transmitter except the power amplifier and preamplifier. Its HIGH signal turns on the circuit, and its LOW signal turns it off.

IF VCO power-down control pin. This pin controls the power-down function of the IF VCO used by the transmitter during the transmission process. Its HIGH signal turns off the circuit, and its LOW signal turns it on.

RF VCO power-down control pin. This pin controls the power-down function of the RF VCO used by the transmitter and receiver. Its HIGH signal turns off the circuit, and its LOW signal turns it on.

Receiver power-down control pin. This pin controls the power-down function of the entire receiver. Its HIGH signal turns on the circuit, and its LOW signal turns it off.

The recommended TDD mode and power saving mode use the following control pins:

* Control level for minimum energy consumption.

BT1074B is a complete RF transceiver, which integrates the functions of receiver, transmitter and local oscillator into a single chip. Because it can be operated in TDD mode, the chip can be used for CT-2 and digital cordless phones, as well as ISM band applications.

The internal transmitter can accept I / Q input from the system interface, and the system interface can also provide AC reference level to the M-REF pin. The on-chip RF filter removes spurious signals before the signal reaches the internal power amplifier. The RF output is a differential signal, so a power combination network and output load are needed to convert it into a single-ended signal interface. By selecting the high / low level of the power control pin, the transmission power mode can be determined so that the output power can be selected within the range of -2dB to + 14dB. The power level can also be set by the external resistance of the REXT1 and REXT2 pins.

In the receiver part, an on-chip bandpass filter (BPF) between the LNA output pin and the input pin of the downconversion mixer can be used to optimize noise performance. The IF output of the first stage is a 150 MHz differential signal, which also requires a power combiner to optimize performance. The two-stage mixer down-converts the IF signal from 150 MHz to 10.7 MHz, which is assisted by an external 139.3 MHz crystal oscillator clock input. The IF amplifier with adjustable gain can provide additional gain with a maximum value of 10dB.

The RF local oscillator and the transmitting IF oscillator in the chip can conveniently provide corresponding signals for working with an external dual PLL frequency synchronizer. RF / IF local oscillators require the use of external adjustment components (see application circuit diagram).

The receiver, transmitter and two local oscillators can all work in the sleep mode through the setting of the power-down control pin on the chip, and its turn-on or turn-off can be controlled by the single-chip microcomputer. For example, in the receiving mode, the microcontroller will turn on the receiver and RF / IF VCO and turn off the transmission function; while in the transmission mode, the microcontroller will turn on the transmitter and RF / IF VCO and turn off the reception function. If necessary, the PA-EN pin will be used to slowly adjust the output level of the power amplifier up or down, and only need to load an externally generated linear ramp voltage on this pin.

Figure 1 internal block diagram

Figure 2 Typical characteristic curve of receiver NF vs. Freq

(The left picture is the temperature change, the right picture is the VDD change)

Figure 3 Typical characteristic curve of transmitter Pout vs. Freq

(The left picture is the temperature change, the right picture is the VDD change)

Fig. 4 Typical characteristic curve of RF VCO Freq vs. Cap

(The left picture is the temperature change, the right picture is the VDD change)

Figure 5 Typical characteristic curve of IF VCO Freq vs. Cap

(The left picture is the temperature change, the right picture is the VDD change)

Figure 6 Block diagram of a digital cordless system

Figure 7 Application circuit diagram

Figure 8 10x10x1.4 64-pin TQFP package

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Product parameters

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