There is an important step between Coarse Placement and Legalization, which is the processing of the Scan Chain. The English name Scan Reorder is literally translated into a scan chain reorganization.
Before talking about Scan Reorder, it is necessary to make some basic knowledge of Scan Chain. Scan chain is actually the content of the testable design (DFT). DFT, Design for test, is actually a design methodology for detecting error sequences. Since the inside of the chip is a black box, it is difficult to control externally. Testers can externally control and observe the signal values ​​of the internal triggers of the circuit through DFT technology. DFT usually requires a separate department to complete, very complicated, and there are special books for reference. The basic concepts can be referred to:
[Introduction to the basic concept of timing analysis - the same "pattern" as flowers]
In the back-end PR, we are more concerned with the Scan Chain in DFT. With it, our chips are more testable. Scan Chain replaces the normal registers used in the chip with scan registers with scan function, which are connected end to end in series, so that additional test functions can be implemented. Where is the scan register special? Let's take a look at its structure diagram:
As can be seen from the above figure, it has three ports of SI, SE and SO than ordinary memory.
1. Where SI, SO is the scan_in and scan_out ends, defines the input and output of a scan chain. Usually, each input will drive a scan chain, and an ouput is also used to observe a scan chain.
2. SE is the scan enable signal, which controls the working mode of the scan cell. It can be seen from the figure that the SE, SI, and D terminals switch the working mode through a Mux. When the SE input is 0, the scan cell works in normal mode, which is equivalent to a normal flop; when the SE input is 1, the scan cell enters scan mode, which is equivalent to a shift register.
The scan cell is usually defined directly in the lib library, and can be checked by get_cells_of_scan_chain.
The picture description may be more vivid. For the entire logic circuit, when the scan chain is not inserted, the circuit diagram is as follows:
After inserting the scan chain, the software will automatically replace the normal flip flop with the scan flip flop (SFF), and connect the SFF to the scan chain, thus implementing the shift scan function, as shown below:
The definition of the scan chain is usually defined by the DEF file. We generally call it scan def. With the following figure, we write the scan DEF statement to illustrate:
SCANCHAINS 1 ; scan chain number
- chain0 scan chain name + START PIN scan_in scan chain starting point + FLOATING represents a separate register unit, in the above figure out_reg_0,_1,_2,_3 are floating units out_reg_0 ( IN SI ) ( OUT Q ) out_reg_1 ( IN SI ) ( OUT Q )
Out_reg_2 ( IN SI ) ( OUT Q ) out_reg_3 ( IN SI ) ( OUT Q )
+ ORDERED Units that need to be put together. In the above figure, out_reg_4 and u_buf are ORDERED units. Circle out_reg_4 ( IN SI ) ( OUT Q ) u_buf ( IN A ) ( OUT Y ) + STOP PIN scan_out ; scan chain END SCANCHAINS
After the concepts are all understood, what do we need to do with the scan chain in the backend?
In fact, after doing the coale placement, the Scan Cell is mostly randomly placed in the order of connection. This will in fact greatly occupy the winding resources. Therefore, before the next step begins, we hope to process the scan chain connection and re-connect without affecting the logic function, thus reducing the trace length. That process of reorganization, we call it Scan Reorder. The whole process can be illustrated by the following two figures:
Before Scan Reorder: You can see that the connection of each scan cell is messy, the terminology is called detour.
After Scan Reorder: Look carefully, there are a lot less traces, and a lot of rules! That's what we hope to get~~ (of course, the premise is that it can't affect the logic function)
If explained by the example of the previous DEF:
After Scan Reorder, it becomes the following circuit connection:
It can be seen that the out_reg_4 and u_buf enclosed by the box are similar to one whole, and the positions are rearranged.
The corresponding Scan DEF information change is:
The DEF format on the left has already been explained in the previous article. Can you understand after the right reorder?
There is a # symbol on the right side, which can be understood as a flag, associated with #ORDERED segment 1 below, to illustrate its position in the FLOATING message.
Finally, we can use report_scan_chains to report the composition of the scan chain, check the rationality with check_scan_chain
Checking Scan Chain scan_segment_88
STOP: u__noram/u_etm/u_fifo/ts_0_lockLD_865264
....
Thru: u_noram/uersistent_cell_0_buf_intsi54506_i/Z
STATUS: VALIDATED, Sequential Length = 524, Instance Count = 524, Partition = partition_1
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