UltraSoC, a leading developer of embedded analytics technology, today announced the full availability of a complete suite of debug and monitoring intellectual property (IP) products for ARM's recently announced AMBA 5 Coherent Hub Interface (CHI) Issue B specification. CHI Issue B is ARM's most advanced bus specification supporting complex system-on-chip (SoC) designs. The monitoring and debugging products provided by UltraSoC are the only products that meet the needs of designers using the CHI Issue B specification.
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As a semiconductor IP product, UltraSoC's monitoring and debugging solutions provide reliable testing and help solve problems for next-generation coherent cache SoC designs based on the CHI Issue B specification, enabling customers to benefit from enhancements to the CHI Issue B specification. Features that enhance its security, data throughput and latency. Dealing with consistency issues is becoming more and more important for designers of complex systems, and UltraSoC was selected as the spokesperson for this topic at the ARM TechCon conference this year, which will take place October 24-26, 2017 in Santa Clara The conference center is held.
By supporting CHI Issue B, UltraSoC continues the path of providing feature-rich, system-level monitoring and debugging solutions that outperform vendor-specific systems such as ARM's CoreSight. Designers can use UltraSoC products as a "full coverage" to get the functionality that their traditional debug systems don't provide, or to use UltraSoC to completely replace them. This holistic approach to debugging is especially beneficial in multicore designs because UltraSoC provides support for all common different CPU architectures and supports open source processor platforms such as RISC-V.
"CHI is an increasingly important protocol that provides key performance for SoC's on-chip inline network; but it is also a challenging standard in design, especially after the launch of the new version of Issue B. "GadgePanesar, chief technology officer of UltraSoC, said. “Simple statistics performance is useful, but not enough; this requires a team like UltraSoC that focuses on monitoring and debugging, and a solution to support it. This is the huge ARM ecosystem. Energy, that is, customers can use third-party solution providers such as UltraSoC to leverage their expertise to help designers quickly and easily solve problems such as consistent design."
Modern SoCs, especially those used in highly complex data centers, enterprise IT systems, or automotive applications, rely on flawless, efficient internal interconnect technology with an on-chip network aggregation center. The development philosophy of the AMBA 5 CHI specification is to ensure that this internal interconnection does not become a bottleneck due to increased traffic and system complexity. Designers can choose how to implement CHI based on power, performance, and chip area requirements. However, in these SoC designs and system choices, there are often various potential problems that may affect system performance, such as traffic issues related to cache coherency. By using UltraSoC's monitoring IP for CHI Issue B, designers of these complex SoCs can quickly check performance while simultaneously diagnosing and predicting such problems.
The CHI Issue B specification integrates a number of major updates that can be directly used to improve latency and throughput, two of the most significant enhancements being far atomic operations and cache hiding. Far-atomic operations support internal interconnects for high-frequency updates of shared data; cache hiding is for low-latency channels, while accelerators or I/O devices are allowed to hide critical data in a CPU cache. For more information on the new AMBA 5 CHI Issue B specification, atomic operations and cache hiding, and other performance enhancements such as direct data transfer, visit the ARM blog.
UltraSoC released the industry's first monitoring and debugging IP product for the earlier (Aussue A) AMBA 5 CHI NoC specification last year, extending its protocol-aware monitor product line for on-chip internal interconnects and supporting both NoC networking networks. Debugging and fine tuning. Since then, UltraSoC has worked closely with a number of leading customers to develop a CHI Issue B solution that can be used to validate protocol implementations to accelerate the overall integration of the chip design and adjust the NoC to the bus. The overhead is minimized.
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